Reduced substrate capacitance high performance SOI process

ABSTRACT

A method for forming a semiconductor substrate. The method comprises the general steps of: providing a handle wafer and a device wafer; implanting at least a first impurity region in a first surface of the device wafer; bonding the first surface of the device wafer to a first surface of the handle wafer with a silicon dioxide layer; removing a portion of the device wafer at the second surface; and forming an epitaxial silicon layer on the second surface of the device wafer. Said step of removing a portion of the device wafer comprises removing a portion of the device layer such that the remaining portion of the device layer has a minimum thickness possible with the technique used for removing.  
     In a further aspect, the invention comprises a silicon on insulator substrate. The substrate comprises a handle wafer; a layer of bonding material; a device wafer, the device wafer including at least one buried impurity region extending from said layer of bonding material upward into said device wafer; and an epitaxial silicon layer provided on a second surface of the device wafer. In a unique aspect, the thickness of the device wafer is defined by the minimum possible thickness utilized by the process to form said device wafer.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The invention relates to a silicon-on-insulator (SOI) structure,a method for forming silicon-on-insulator substrates, and devices formedin such substrates. In particular, the invention concerns bipolardevices formed in an improved SOI substrate, and a method for forming abipolar device in a silicon-on-insulator substrate.

[0003] 2. Description of the Related Art

[0004] Integrated circuit devices generally comprise a number of activedevices formed on and in a semiconductor substrate, which are coupled byat least one layer of conducting material, such as polysilicon or metal.In manufacturing integrated circuits, while bulk silicon wafer(s) arecommonly used, a number of advantages accompany the use ofsilicon-on-insulator substrates. In general, a silicon-on-insulatorsubstrate comprises a layer of device silicon overlying a layer ofinsulating material. SOI substrates provide the advantages of increasedpacking densities and low parasitic capacitances in certain types ofdevices manufactured on such substrates. In bipolar devices,construction on silicon-on-insulator substrates provides a number ofdistinct advantages.

[0005] One technique for constructing silicon-on-insulator substrates isto bond two bulk silicon substrates to each other; a so-called “device”substrate is bonded to a so-called “handle” or “bonding” substrate byany number of techniques. Normally, bonding is done using blankunprocessed silicon device wafers on oxidized silicon handle wafers.This method has achieved wide acceptance in the industry due to itssimplicity, robustness and high yield. Once the device wafer is bondedto the handle wafer, a device wafer is generally etched or polished backto obtain a desired thickness for the wafer. Further polishing andcleaning generates a quality silicon-on-insulator wafer for devicefabrication.

[0006] One disadvantage of this method is that the cost of the startingmaterial bonded wafers is relatively high.

[0007] In forming bipolar devices, it is advantageous to provide buriedlayers of an impurity at the bottom surface of the substrate in order toreduce the resistance of collector bulk regions. In many current SOIprocesses, to provide the buried layers, after a bonded wafer isconstructed, a field oxide is grown or deposited on the wafer. Thisoxide is then patterned using photolithography and high dose implants ofan N-type or P-type conductivity, as the case may be, are implanted todefine the N-type or P-type buried layers. The implantation is ofsufficient force to place the buried layers below the surface of thedevice wafer substrate at a desired depth and concentration so thatsubsequent processing will result in migration of the impurity to itsdesired location in the substrate through diffusion. This methodrequires expensive equipment for high energy implants and thinner devicelayer SOI wafers. Both factors tend to increase cost. Alternatively, theimplants will be made into the surface of the device wafer followingbonding, and an epitaxial layer is then formed on the surface of thedevice (following removal of the resist pattern and oxide). Duringepitaxial deposition, the implanted buried layers are subject to thermalforces that diffuse these layers in all directions.

[0008] The resulting structure is shown in FIG. 1. In FIG. 1, a handlesubstrate 10 is coupled to a device substrate 20 by an oxide layer 30.Device substrate 20 has been ground or etched back from its originalthickness to a thickness dT of about 2 μm. An epitaxial layer 40 isshown on the upper surface 25 of device substrate 20. An N+ buriedregion 50 and a P+ upper buried region 55 are shown as being presentbelow the surface 60 of silicon-on-insulator substrate 100. As shown inFIG. 1, buried layers diffuse both upward into the epitaxial layer anddownward into the device wafer 20. These buried layers will definecollector regions of a complementary bipolar silicon-on-insulatordevice.

[0009] After formation of the buried regions 50,55, the SOI substratehas a parasitic substrate capacitance that varies as a function of thedepth of the substrate. In FIG. 2, the left side of the horizontal scaleindicates the dopant concentration levels for a typical bipolartransistor and the variation of concentrations and junctions throughepilayer and device wafer down toward the silicon dioxide 30, at theright side of the horizontal scale. As shown therein, in the substrateof the prior art, the buried layer concentration profile peaks at thejuncture between the epitaxial layer and the remaining portion of thedevice wafer.

[0010] The presence of buried layers at the interface of the epitaxiallayer and the handle wafer 20 creates a large diffused buried layer.This increases the total tub depth thickness to T+dT, where dT is thethickness of the remaining portion of the device wafer. Typically, thisthickness is about 2 μm. This additional 2 μm contributes to highersubstrate capacitances, saturation voltages, and lowers the speed ofdevices formed in such substrates. Effectively, bipolar transistorsformed in such substrates have compromised performance due to thepresence of buried layers at the top of the device wafer 20. Inaddition, that portion of the handle wafer 20 below the concentrationpeak having a thickness dT is wasted in the SOI substrate.

SUMMARY OF THE INVENTION

[0011] The invention, roughly described, comprises in one aspect amethod for forming a semiconductor substrate. The method comprises thegeneral steps of: providing a handle wafer and a device wafer;implanting at least a first impurity region in a first surface of thedevice wafer; bonding the first surface of the device wafer to a firstsurface of the handle wafer with a silicon dioxide layer; removing aportion of the device wafer at the second surface; and forming anepitaxial silicon layer on the second surface of the device wafer.

[0012] One or more impurity regions may be implanted into the devicewafer utilizing both N and P type impurities. The bonding step maycomprise the substeps of forming a bonding oxide on the surface of thehandle wafer; coupling the first surface to the bonding oxide; andheating the handle wafer and the device wafer.

[0013] In a unique aspect, said step of removing a portion of the devicewafer comprises removing a portion of the device layer such that theremaining portion of the device layer has a minimum thickness possiblewith the technique used for removing.

[0014] In a further aspect, the invention comprises a silicon oninsulator substrate. The substrate comprises a handle wafer; a layer ofbonding material; a device wafer, the device wafer including at leastone buried impurity region extending from said layer of bonding materialupward into said device wafer; and an epitaxial silicon layer providedon a second surface of the device wafer. In a unique aspect, thethickness of the device wafer is defined by the minimum possiblethickness utilized by the process to form said device wafer.

BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The invention will be described with respect to the particularembodiments thereof. Other objects, features, and advantages of theinvention will become apparent with reference to the specification anddrawings in which:

[0016]FIG. 1 is a cross-section of a silicon-on-insulator substratehaving buried regions formed in accordance with the method of the priorart.

[0017]FIG. 2 is a graph representing concentration levels as a functionof depth for the structure shown in FIG. 1.

[0018] FIGS. 3-6 are cross-sections of the formation of asilicon-on-insulator substrate in accordance with the method of thepresent invention.

[0019]FIG. 7 is a graph representing the concentration level as afunction of depth for the substrate of the present invention.

[0020] FIGS. 8-11 are cross-sections of a silicon-on-insulator substrateillustrating the construction of complementary bipolar transistors inthe silicon-on-insulator substrate.

[0021]FIG. 12 is a flow chart of the method of the invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0022] Described below are a method for forming a silicon-on-insulatorsubstrate, a method for forming a bipolar transistor structure, and abipolar transistor structure formed on a silicon-on-insulator substratein accordance with the present invention. Significant gains in deviceperformance are achieved in the device of the present invention asburied layers are fabricated at the bottom of the device layer in asilicon-on-insulator substrate. With buried layers present at the bottomof the device layer, the effective device tub depth is smaller than thatshown with respect to the prior art. In the method of the presentinvention, buried layers only diffuse upward, as they are initiallypositioned to encounter the bonding oxide which prevents a downwarddiffusion path of the buried layer.

[0023] Hence, the method of the present invention results in a small yethighly conductive buried layer profile complemented with a reduction intub depth thickness. In one aspect, this reduction in tub depth is thesame as the thickness of the silicon-on-insulator layer or about 2 μm.Since the tub depth is smaller than conventional processes by about 2μm, superior device characteristics are realized in terms of reducedsubstrate capacitance, lower saturation voltages, and higher speeds onboth the device and circuit levels.

[0024] The method of the invention is illustrated in flow chart form inFIG. 12 and throughout the specification, reference will be made to thesteps illustrated therein.

[0025] FIGS. 3-11 illustrate cross-sections of a device under formationin accordance with the present invention. Shown in FIG. 3 is asemiconductor substrate 200, which may comprise a bulk silicon substratehaving a background doping concentration of an N-type or P-typeimpurity, and having a crystal lattice structure of 1-0-0. Substrate 200will eventually form the device substrate in the SOI substrate portionof the invention. For purposes of the description of the invention, inone embodiment, substrate 200 has a P-type background dopingconcentration of 10¹⁶ atm/cm⁻³.

[0026] Initially, the N and P buried regions are formed in substrate 200(steps 500 and 502 in FIG. 12). In order to form an N-type buried region210 (step 500), a masking layer (not shown) is formed on the surface 215of substrate 200 and patterned to open a window (not shown) over thearea of surface 215 where region 210 is to be formed. The mask layer maybe a photoresist layer of any known type, or may be any of a number ofalternative masking layers such as, for example, silicon dioxide orsilicon nitride. In either case, the mask layers are formed andpatterned in accordance with well-known techniques for such layers.

[0027] An implant of an N-type impurity such as arsenic or phosphorousis then made into substrate 200 at an energy in the range of about 25 to180 KeV to provide a resulting concentration of about 10¹⁷ to 10²¹atm-cm⁻³ forming region 210.

[0028] Subsequently, the N region masking layer is removed and a P-typeburied region is formed (step 502). A second mask layer (not shown) isfirst formed and again may be any of the type mentioned above, formedand patterned in accordance with well-known techniques in order to opena window (not shown) in the mask layer. An implant at an energy of 25 to180 of a P-type impurity such as boron forms region 220 with aconcentration of about 10¹⁷-10²¹ atm/cm⁻³ in substrate 215.Subsequently, the P-type buried region mask is stripped, and substrate200 with regions 210 and 220 formed therein will undergo a pre-bondcleaning (step 504). The resulting structure is shown in FIG. 3.

[0029] In one aspect, the cleaning process of step 504 proceeds firstwith a chemical cleaning of the wafers, followed by a megasonic cleaningof the wafers, and finally drying of the wafers utilizing one of anumber of commercial drying apparatus which performs marangoni drying.The cleaning and drying process may, in one embodiment, be followed by ahigh temperature anneal to cure silicon damage caused by the implantsused for regions 210,220, as discussed in co-pending application Ser.No. 09/294,564 entitled SILICON TO OXIDE WAFER BONDING PROCESS, InventorSameer Parab, filed Apr. 20, 1999, assigned to the Assignee of thepresent application.

[0030] As shown in FIG. 4, substrate 200 is thereafter bonded (step 506)to a handle wafer 250. As shown in FIG. 4, in this embodiment of theinvention, a bonding oxide 275 is used at the interface of device wafer200 and handle wafer 250. However, the procedure for bonding the devicewafer 200 to handle wafer 250 may be any of a number of bondingtechniques such as those described in Mazzera, “SOI By Wafer Bonding: AReview,” ECS: SOI Technology and Devices, Volume 90-6,1990.

[0031] Generally, bonding oxide 275 is formed on handle wafer 250 priorto bonding by a thermal oxidation or deposition oxidation processresulting in oxide 275 having a thickness of about 0.5 μm to 2 μm, andbonding occurs through surface coupling and annealing of the bondedwafer shown in FIG. 4 at a temperature of 300°-1100° C. for a period ofone to ten hours to ensure adequate bonding strength between the handlewafer 200 and the device wafer 250. It should be recognized theseparameters may change based on oxide thickness and other factors.

[0032] Following bonding, at step 508 the device wafer 200 is ground oretched to form a thinner device wafer 200 a as shown in FIG. 5. Currentcommercial grinding techniques are accurate only to about +/−0.5 μmsurface smoothness tolerance. Hence, in accordance with the invention,layer 200 a is ground back to a minimum thickness possible in accordancewith the grinding tool being used, or the etch process which isutilized, to thin the device wafer 200. For a grinding process with anaccuracy of 0.5 μm, this thickness is about 2.0 μm. The method providesparticular advantages when used with commercial grinding and polishingprocesses, which are lower-cost than more accurate etching processes. Itshould be recognized that the thicknesses set forth herein areexemplary, as is the accuracy of the grinding process, and the actualvalues will vary according to the thinning process being utilized. Forpurposes of the invention, it is only critical that some portion of thedevice layer containing regions 210 and 220 remain following the processused to thin the wafer 200. Hence, future grinding processes moreaccurate than the 0.5 μm current technology may be utilized inaccordance with the present invention, as may etch back processes, andhence dT may be thinner than 2 μm. The resulting ground layer 200 a isshown in FIG. 5.

[0033] Following thinning, the device wafer is polished and cleaned(step 510) to ensure as smooth a surface as possible for subsequentepitaxial layer deposition.

[0034] Optionally, at this point of the process, a P collector and Ncollector modulation implant, utilized in the construction of bipolardevices, may be performed to ensure proper migration of the buriedregion and correct collector profiles. The N and P modulation implantregions (not shown) will be formed on to the buried regions 210,220,respectively, in accordance with well-known techniques. For example, anN-type collector implant modulation mask (step 512) will be formed inaccordance with the foregoing descriptions to allow an N-type impurityimplant at an energy of about 25 KeV to 180 KeV having a concentrationof 10¹⁵-10¹⁷ to be made adjacent to or superimposed on the N region 210.Similarly, at step 524 a P collector modulation mask and implant may beutilized with respect to region 220. The modulation implants formregions which are generally located above regions 210 and 220 in orderto ensure correct concentrations between the buried regions 210,220 andthe collector which will be subsequently formed in the transistorstructure.

[0035] Next, as shown in FIG. 12 at step 516 and in cross-section atFIG. 6, an epitaxial silicon layer 300 is formed on the surface 215 a ofdevice wafer 200 a. Epitaxial silicon layer 300 may be formed to adesired thickness by placing substrate 290 in a silane or siliconchloride atmosphere at a temperature in the range of 300°-1,200° C. inaccordance with conventional techniques. Alternatively, molecular beamepitaxy may be used to deposit the epitaxial layer at a pressure ofabout 10⁻⁹ to 10⁻¹¹ Torr and a temperature in a range of 450°-750° C. Ineither case, lower temperature processes are desirable to reduce anydiffusion of regions 210 and 220.

[0036] During epitaxial layer deposition some diffusion of regions 210and 220 will occur due to the heating of the substrate which occursduring this process. Diffusion of regions 210,220 will occur inaccordance with well-known diffusion properties of the particularimpurity used for the implant. FIG. 6 illustrates one case of suchdiffusion wherein regions 210 and 220 are formed in device layer 200 aand remain solely within layer 200 a. It should be recognized thatburied regions 210,220 may migrate into epitaxial layer 300 in caseswhere device layer 200 a has been thinned to a sufficient level thatdiffusion of regions 210 and 220 will allow such migration.

[0037] The resulting structure 290 shown in FIG. 6 is asilicon-on-insulator substrate with buried impurity regions having animproved substrate capacitance profile over that of the prior art. Shownin FIG. 7 is the concentration profile of the substrate shown in FIG. 6.As shown therein, the substrate of the present invention is thinner thanthe prior art SOI substrate by a thickness of dT; the material whichformerly comprised thickness dT in the device wafer 20 of the prior artis no longer present in this device. The resulting device tub region hasa thickness T. In accordance with the present invention, this reducedthickness reduces the substrate capacitance and saturation voltages whenburied layers or high conductivity regions are present at the bottom ofthe silicon insulator layer.

[0038] Following formation of the substrate 290 as shown in FIG. 6, acomplementary bipolar transistor structure may be formed in accordancewith a further aspect of the invention as shown in FIGS. 8-11.

[0039] Initially, at step 520 (FIG. 12), field oxide layer 310 (shown inFIG. 8) is formed over the surface of epitaxial layer 300. Field oxide310 may be a CVD deposited oxide layer or a thermally-grown oxide layerformed in accordance with well-known techniques.

[0040] Subsequently, active device areas, where active components are tobe formed in the substrate, are isolated by one of several methods ofactive area isolation (step 520). In one well-known embodiment, trenchisolation may be utilized. There are a number of well-known processesfor fabricating trench isolation. In one method, a trench is etched inepitaxial layer 300 and device layer 200 a, and the trench filled withan isolation material. The trench is formed by deposition of a markinglayer followed by patterning of the trench mask and a trench etch usinga directional dry etch technique such as reactive ion etching ofepitaxial layer 300 and device wafer 200 a. The trench etch is followedby a trench fill of, for example, a layer of deposited oxide followed bya thicker, highly-doped polysilicon layer. The trench fill may befollowed by subsequent thermal processing. Trench isolation is shown inblock form at reference numeral 320 in FIG. 8A.

[0041] An alternative method of isolating is shown in FIG. 8B. Junctionisolation region 325 is formed through the use of a masking layer suchas a photoresist layer patterned in accordance with well-knowntechniques to open windows in the layer to allow a junction implant anddiffusant of a P or N conductivity type (opposite to the tub in whichthe device is formed) deep into both epitaxial layer 300 and devicelayer 200 a.

[0042] Next, the N-type and P-type collectors are formed (steps 530 and532) by utilizing a series of masking, patterning, and implant (and/ordiffusion) steps. The N-type and P-type collectors 311,312 areillustrated as shaded diffusions in FIG. 9. It will be understood by oneof average skill in the art that their formation is required for properoperation of a bipolar transistor. An exemplary P-type collector implantwill be performed at an energy of about 25 to 180 KeV to form acollector region having a doping concentration of about 10¹⁵-10¹⁷atm/cm⁻³.

[0043] Next, at steps 540 and 542, N-type and P-type sinkers 330,332 areformed in the structure 290 as shown in FIG. 9. Once again, a series ofmasking and implant steps are used to form the sinker regions 330,332.Again, any of a number of types of photoresist, silicon dioxide, orsilicon nitride masks are deposited and patterned in accordance withconventional methods for the resist layer, and an impurity implant at anenergy of 25 to 180 KeV to form N sinker region 330 with an arsenic orphosphorous concentration of 10¹⁷-10²¹ cm⁻³, and 25 to 180 KeV to form Psinker region 332 with a boron concentration of 10¹⁷-10²¹ cm⁻³ are used.

[0044] A drive-in diffusion at step 544 follows the sinker implant tocorrectly position the sinker and collectors. The resulting structure isshown in FIG. 10. This diffusion step may comprise heating the substrateat a temperature of 1000-1250° or for an adequate period of time. Thedrive-in step for the collectors and sinkers has the side effect thatthe buried regions 210,220 will diffuse upward further into thesubstrate 290. In FIG. 10, the buried regions are shown as contact inthe junction between the epitaxial layer and the device substrate. Asnoted above, it will be recognized that the diffusion of the buriedregions may, in some embodiments, proceed through this junction into theepitaxial layer or may not reach this junction, depending on the devicebeing formed.

[0045] As noted above, the method of the present invention isillustrated in flow chart form in FIG. 12. To avoid unnecessaryreplication of similar cross-sectional figures, each masking, etching,implant and diffusion step is not shown in cross-section. However,application of each step in FIG. 12 will be readily apparent to one ofaverage skill in the art in view of the foregoing.

[0046] Next, at step 546 an active region for the complementarytransistor will be formed in the substrate. If, for example, the devicewafer 200 a and epitaxial layer 300 are formed having a P-typebackground doping concentration, an N-type implant will be utilized toform the complementary transistor. Once again, a series of masking andetching steps is utilized. First, an active mask layer will be providedover the substrate and the mask patterned to form a window above theactive area to be implanted.

[0047] Subsequently, at steps 548,550, the respective base regions350,352 for the bipolar transistors will be formed. First an N-base maskwill be formed and patterned, and an N-type implant provided into area350 where the N-type base is formed. This implant is typically ofphosphorous at an energy of 120 KeV to a depth of about 1.5 μm, and at aconcentration of 10¹⁸ atm/cm⁻³. Next, a diffusion step is used to drivethe dopant into the structure 290 to complete the N-type base.

[0048] Next, a P-base region 352 is formed through a mask, an implantand diffusion in a manner equivalent to the N-base region formation. TheP-type implant is typically boron at an energy of about 80 KeV to adepth of about 1.7 μm, and at a concentration of 10¹⁷ atm/cm⁻³.

[0049] Next, at step 552 a capacitor oxide formation is performed. Thecapacitor oxide is used to form a semiconductor based capacitor elementin the substrate which may comprise a component of integrated circuit ofwhich the complementary bipolar structure shown in FIGS. 1-12 is a part,in a different portion of the substrate (not shown). This capacitoroxide formation may take place by any of a number of well-known methods,including thermal oxidation of selectively exposed silicon regions.Capacitor oxide formation is followed by an annealing at step 554.

[0050] Following this annealing step, a low temperature oxide depositionat step 556 is performed over the epitaxial layer surface to form anoxide as shown in FIG. 11 (after patterning) at reference numeral 380.

[0051] Following deposition of the low temperature oxide 380, the N-andP-type emitters 392,394 for the respective transistors are formed atstep 558,560. Once again, for each emitter formation, a masking layer isformed and patterned in accordance with well-known techniques. Animplant is made into the surface of the epitaxial layer, and a diffusionstep performed to place the emitter impurity region in the correctlocation within the active region 375. Optionally additional baseimplants 393,395 may be provided in regions 350,352, respectively.

[0052] Finally, at step 562 metal contacts 390 are deposited and formedto interconnect regions of the complementary bipolar transistor withother components of the integrated circuit as shown in FIG. 11. Themetal deposit layer is etched following deposition in accordance withwell-known techniques to form contacts 390 as shown in FIG. 11. Finally,a passivation layer 398 covering the metal etch contacts is deposited atstep 564.

[0053] The method and structure of the present invention provides variedN- and P-type buried layers for bipolar device formation at the bottomof a silicon-on-insulator layer. The method provides a means ofintroducing high conductivity regions of N- and P-types into the bottomof the silicon-on-insulator layer. The total tub thickness of the finaldevice is reduced by introducing the buried layers prior to bonding. Oneor both types of impurity regions can be provided. As a result, thesubstrate capacitance due to reduced tub thickness and the introducedburied layers provides an improved bipolar device. In addition, thedevice has increased operational speed. A direct silicon to silicondioxide bond is utilized.

[0054] In addition, collector layer modulation after silicon to silicondioxide bonding and prior to epitaxial silicon deposition is a benefitof the present invention. Additional implants to grade the buried regionprior to epitaxial deposition helps to achieve lower saturation voltagesfor the bipolar transistors formed in accordance with this method. Themethod of the invention allows for trench isolation or N- or P-typejunction isolation depending on the nature of the device underconstruction. Silicon etch trenches of any shape and size may beutilized. In addition, the trenches may be refilled with combinations ofsilicon dioxide, silicon nitride and high conductivity polysilicon of N-or P-type conductivity.

[0055] These and other advantages of the present invention will bereadily apparent to one of average skill in the art. The inventionprovides particular advantages of a low-cost method to provide thin, lowcapacitance SOI substrates by allowing low-cost processes, such asgrinding, to be used to thin device wafers. All such features andadvantages are intended to be within the scope of the invention as setforth herein and as defined by the following claims.

What is claimed is:
 1. A process for manufacturing a silicon oninsulator substrate with buried implant layers, comprising the steps of:(A) providing a handle wafer and a device wafer; (B) implanting at leasta first impurity region in a first surface of the device wafer; (C)bonding the first surface of the device wafer to a first surface of thehandle wafer with a silicon dioxide layer; (D) removing a portion of thedevice wafer at the second surface; and (E) forming an epitaxial siliconlayer on the second surface of the device wafer.
 2. The method of claim1 wherein said step (B) includes implanting said at least first and asecond impurity region in the first surface of the substrate.
 3. Themethod of claim 1 wherein said step (B) comprises implanting an n-typeimpurity to a junction depth of less than 1 micron.
 4. The method ofclaim 1 wherein said step (B) comprises implanting an p-type impurity ata junction depth of less than 1 micron.
 5. The method of claim 1 whereinsaid step (C) comprises: forming a bonding oxide on the surface of thehandle wafer; coupling the first surface to the bonding oxide; andheating the handle wafer and the device wafer.
 6. The method of claim 5wherein said step of forming a bonding oxide comprises forming an oxidehaving a thickness in the range of 0.5 to 2 microns.
 7. The method ofclaim 1 wherein said step (D) comprises removing a portion of the devicelayer such that the remaining portion of the device layer has a minimumthickness possible with the technique used for removing.
 8. The methodof claim 7 wherein said step (D) comprises grinding the device layer. 9.The method of claim 7 wherein said step (D) comprises etching the devicelayer.
 10. The method of claim 1 wherein said step (D) includes removinga portion of said at least one implant region during said removing step.11. The method of claim 1 wherein said step (E) comprises growing alayer of silicon in a silane containing atmosphere.
 12. The method ofclaim 11 wherein said step (E) includes diffusing a portion of said atleast on impurity region into said epitaxial layer.
 13. The method ofclaim 1 wherein said step (D) results in a remaining portion of thedevice wafer having a thickness of about 1-2 microns.
 14. The method ofclaim 13 wherein said step (E) comprises forming said epitaxial layerwith an upper surface such that the distance between the upper surfaceof the epitaxial layer and the bonding oxide is about 4-5 microns.
 15. Aprocess for manufacturing a substrate having low substrate capacitanceand lower saturation voltages with buried impurity regions, comprisingthe steps of: providing a handle wafer having a first and a secondsurface; providing a device wafer having a first and a second surface;sequentially: (A) forming implant regions in the first surface of thedevice wafer; (B) forming a bonding layer on the first surface of thehandle wafer; (C) coupling the first surface of the device wafer to thebonding layer; (D) removing portions of the device wafer from the secondsurface of the device wafer; and (E) forming an epitaxial silicon layeron the second surface of the device substrate.
 16. The method of claim15 wherein said step (a) comprises implanting an n-type impurity at anenergy of 25-180 KeV to a concentration of about 10¹⁷-10²¹ atm/cm⁻³. 17.The method of claim 15 wherein said step (a) comprises implanting anp-type impurity at an energy of 25-180 KeV to a junction depth of about10¹⁷-10²¹ ⁶ atm/cm-⁻³.
 18. The method of claim 15 wherein said step (c)comprises: coupling the first surface to the bonding oxide; and heatingthe handle wafer and the device wafer.
 19. The method of claim 18wherein said step of forming a bonding oxide comprises forming an oxidehaving a thickness in the range of 0.5 μm to 2.0 μm.
 20. The method ofclaim 15 wherein said step (d) comprises removing a portion of thedevice layer such that the remaining portion of the device layer has aminimum thickness possible with the technique used for removing.
 21. Themethod of claim 15 wherein said step (d) comprises grinding andpolishing the device layer.
 22. The method of claim 15 wherein said step(d) includes removing a portion of said at least one implant regionduring said removing step.
 23. The method of claim 15 wherein said step(e) comprises growing a layer of silicon in a silane containingatmosphere.
 24. The method of claim 23 wherein said step (e) includesdiffusing a portion of said at least on impurity region into saidepitaxial layer.
 25. The method of claim 15 wherein said step (d)results in a remaining portion of the device wafer having a thickness ofabout 1-2 microns.
 26. A silicon on insulator substrate, comprising: ahandle wafer; a layer of bonding material; a device wafer, the devicewafer including at least one buried impurity region extending from saidlayer of bonding material upward into said device wafer; and anepitaxial silicon layer provided on a second surface of the devicewafer.
 27. The substrate of claim 26 wherein the thickness of the devicewafer is defined by the minimum possible thickness utilized by theprocess to form said device wafer.
 28. The substrate of claim 26 whereinthe thickness of the device wafer is in a range of about 1-3 microns.29. The substrate of claim 26 wherein a portion of said implant regionis provided in said epitaxial layer.
 30. The substrate of claim 26wherein a measure of the capacitance of said substrate is greater thanor equal at said oxide and said surface.
 31. The substrate of claim 26wherein the buried region has a doping concentration gradient which isgreater at a point adjacent to the bonding oxide than at a point fartheraway from the bonding oxide.
 32. The substrate of claim 26 wherein theburied region extends into the epitaxial layer.
 33. The substrate ofclaim 26 wherein the device layer has a thickness and the buried regionhas a depth in said device region of at least one half the thickness ofthe device layer.
 34. A semiconductor device comprising: a handle wafer;a layer of bonding material; a device wafer, the device wafer includingat least one buried impurity region extending from said layer of bondingmaterial upward into said device wafer; an epitaxial silicon layerprovided on a second surface of the device wafer; at least one activeregion provided in the device wafer and epitaxial silicon layer; and aburied region provided in the device wafer having a greaterconcentration of dopant atoms at a point in the device wafer closer tothe bonding material than at a second point farther from the bondingmaterial.
 35. The semiconductor device of claim 34 wherein the deviceactive region includes: a base region; a collector region; and anemitter region.
 36. The semiconductor device of claim 35 wherein theactive region further includes a surface, and the device furtherincludes a first metal interconnect formed on the surface coupled tosaid collector, a second metal interconnect coupled to said emitter, anda third metal interconnect coupled to said base region.
 37. Thesemiconductor device of claim 34 further including a sinker regionintersecting said buried region.